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Freescale Semiconductor Data Sheet: Advance Information
Document Number: MCF54455 Rev. 3, 12/2008
MCF54455
MAPBGA-256 17mm x 17mm TEPBGA-360 23mm x 23mm
MCF5445x ColdFire(R) Microprocessor Data Sheet
Features * Version 4 ColdFire(R) Core with MMU and EMAC * Up to 410 Dhrystone 2.1 MIPS @ 266 MHz * 16-KBytes instruction cache and 16-KBytes data cache * 32-KBytes internal SRAM * Support for booting from SPI-compatible flash, EEPROM, and FRAM devices * Crossbar switch technology (XBS) for concurrent access to peripherals or RAM from multiple bus masters * 16-channel DMA controller * 16-bit 133-MHz DDR/mobile-DDR/DDR2 controller * USB 2.0 On-the-Go controller with ULPI support * 32-bit PCI controller @ 66MHz * ATA/ATAPI controller * 2 10/100 Ethernet MACs * Coprocessor for acceleration of the DES, 3DES, AES, MD5, and SHA-1 algorithms * Random number generator * Synchronous serial interface (SSI) * 4 periodic interrupt timers (PIT) * 4 32-bit timers with DMA support * DMA-supported serial peripheral interface (DSPI) * 3 UARTs * I2C bus interface
This document contains information on a new product. Specifications and information herein are subject to change without notice. (c) Freescale Semiconductor, Inc., 2008. All rights reserved.
Table of Contents
1 2 3 MCF5445x Family Comparison . . . . . . . . . . . . . . . . . . . . . . . .4 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . . .5 3.1 Analog Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . .5 3.2 Oscillator Power Filtering . . . . . . . . . . . . . . . . . . . . . . . .6 3.3 Supply Voltage Sequencing . . . . . . . . . . . . . . . . . . . . . .6 3.3.1 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . .7 3.3.2 Power-Down Sequence . . . . . . . . . . . . . . . . . . . .7 Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .7 4.1 Signal Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4.2 Pinout--256 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . .15 4.3 Pinout--360 TEPBGA. . . . . . . . . . . . . . . . . . . . . . . . . .16 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 5.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .17 5.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .18 5.3 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 5.4 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .19 5.5 ClockTiming Specifications . . . . . . . . . . . . . . . . . . . . . .20 5.6 Reset Timing Specifications . . . . . . . . . . . . . . . . . . . . .22 5.7 FlexBus Timing Specifications . . . . . . . . . . . . . . . . . . .23 5.8 SDRAM AC Timing Characteristics. . . . . . . . . . . . . . . .25 PCI Bus Timing Specifications . . . . . . . . . . . . . . . . . . 27 5.9.1 Overshoot and Undershoot . . . . . . . . . . . . . . . 28 5.10 ULPI Timing Specifications . . . . . . . . . . . . . . . . . . . . . 29 5.11 SSI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . 30 5.12 I2C Timing Specifications . . . . . . . . . . . . . . . . . . . . . . 32 5.13 Fast Ethernet Timing Specifications . . . . . . . . . . . . . . 33 5.13.1 Receive Signal Timing Specifications . . . . . . . 33 5.13.2 Transmit Signal Timing Specifications . . . . . . . 34 5.13.3 Asynchronous Input Signal Timing Specifications34 5.13.4 MII Serial Management Timing Specifications . 35 5.14 32-Bit Timer Module Timing Specifications . . . . . . . . . 35 5.15 ATA Interface Timing Specifications. . . . . . . . . . . . . . . 36 5.16 DSPI Timing Specifications . . . . . . . . . . . . . . . . . . . . . 36 5.17 SBF Timing Specifications. . . . . . . . . . . . . . . . . . . . . . 38 5.18 General Purpose I/O Timing Specifications. . . . . . . . . 39 5.19 JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . 40 5.20 Debug AC Timing Specifications . . . . . . . . . . . . . . . . . 42 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.9
4
5
6 7 8 9
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 2 Freescale Semiconductor
MCF54455
JTAG Version 4 ColdFire Core 16K Instruction Cache 16K Data Cache EMAC BDM Oscillator PLL
2 FECs
USB OTG
32K SRAM
Hardware Divide
CAU
MMU
eDMA
PCI
Serial Boot
Crossbar Switch (XBS)
Peripheral Bridge ATA DSPI SSI I2C RNG RTC GPIO
SDRAM Controller
FlexBus
EPORT
Watchdog
2 INTCs
4 PITs
3 UARTs
4 DMA Timers LEGEND
ATA BDM CAU DSPI eDMA EMAC EPORT FEC GPIO I2 C
- Advanced Technology Attachment Controller - Background debug module - Cryptography acceleration unit - DMA serial peripheral interface - Enhanced direct memory access - Enchance multiply-accumulate unit - Edge port module - Fast Ethernet Controller - General Purpose Input/Output Module - Inter-Intergrated Circuit
INTC JTAG MMU PCI PIT PLL RNG RTC SSI USB OTG
- Interrupt controller - Joint Test Action Group interface - Memory management unit - Peripheral Component Interconnect - Programmable interrupt timers - Phase locked loop module - Random Number Generator - Real time clock - Synchronous Serial Interface - Universal Serial Bus On-the-Go controller
Figure 1. MCF54455 Block Diagram
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 3
MCF5445x Family Comparison
1
MCF5445x Family Comparison
Table 1. MCF5445x Family Configurations
Module MCF54450 * MCF54451 * MCF54452 * MCF54453 * MCF54454 * MCF54455 *
The following table compares the various device derivatives available within the MCF5445x family.
ColdFire Version 4 Core with EMAC (Enhanced Multiply-Accumulate Unit) Core (System) Clock Peripheral Bus Clock (Core clock / 2) External Bus Clock (Core clock / 4) Performance (Dhrystone/2.1 MIPS) Independent Data/Instruction Cache Static RAM (SRAM) PCI Controller Cryptography Acceleration Unit (CAU) ATA Controller DDR SDRAM Controller FlexBus External Interface USB 2.0 On-the-Go UTMI+ Low Pin Interface (ULPI) Synchronous Serial Interface (SSI) Fast Ethernet Controller (FEC) UARTs I2C DSPI Real Time Clock 32-bit DMA Timers Watchdog Timer (WDT) Periodic Interrupt Timers (PIT) Edge Port Module (EPORT) Interrupt Controllers (INTC) 16-channel Direct Memory Access (DMA) General Purpose I/O Module (GPIO) JTAG -- IEEE 1149.1 Test Access Port Package
(R)
up to 240 MHz up to 120 MHz up to 60 MHz up to 370
up to 266 MHz up to 133 MHz up to 66 MHz up to 410 16 KBytes each 32 KBytes
* -- -- * * * * * 1 3 * * * 4 * 4 * 2 * * *
* * -- * * * * * 1 3 * * * 4 * 4 * 2 * * *
* -- -- * * * * * 2 3 * * * 4 * 4 * 2 * * *
* * -- * * * * * 2 3 * * * 4 * 4 * 2 * * *
* -- * * * * * * 2 3 * * * 4 * 4 * 2 * * *
* * * * * * * * 2 3 * * * 4 * 4 * 2 * * *
256 MAPBGA
360 TEPBGA
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 4 Freescale Semiconductor
Ordering Information
2
Ordering Information
Table 2. Orderable Part Numbers
Freescale Part Number MCF54450VM180 MCF54450 Microprocessor MCF54450VM240 256 MAPBGA MCF54451CVM180 MCF54451 Microprocessor MCF54451VM240 MCF54452CVR200 MCF54452 Microprocessor MCF54452VR266 MCF54453CVR200 MCF54453 Microprocessor MCF54453VR266 360 TEPBGA MCF54454CVR200 MCF54454 Microprocessor MCF54454VR266 MCF54455CVR200 MCF54455 Microprocessor MCF54455VR266 266 MHz 0 to +70 C 266 MHz 200 MHz 0 to +70 C -40 to +85 C 200 MHz -40 to +85 C 266 MHz 0 to +70 C 266 MHz 200 MHz 0 to +70 C -40 to +85 C 240 MHz 200 MHz 0 to +70 C -40 to +85 C 180 MHz -40 to +85 C 240 MHz Description Package Speed 180 MHz 0 to +70 C Temperature
3
3.1
Hardware Design Considerations
Analog Power Filtering
To further enhance noise isolation, an external filter is strongly recommended for the analog VDD pins (VDD_A_PLL, VDD_RTC). The filter shown in Figure 2 should be connected between the board IVDD and the analog pins. The resistor and capacitors should be placed as close to the dedicated analog VDD pin as possible. The 10- resistor in the given filter is required. Do not implement the filter circuit using only capacitors. The analog power pins draw very little current. Concerns regarding voltage loss across the 10-ohm resistor are not valid.
10 Board IVDD 10 F 0.1 F Analog VDD Pin
GND
Figure 2. System Analog VDD Power Filter
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 5
Hardware Design Considerations
3.2
Oscillator Power Filtering
10 VDD_OSC 1 F VSS_OSC 100 MHz GND 0.1 F EVDD Pin
Figure 3 shows an example for isolating the oscillator power supply from the I/O supply (EVDD) and ground.
Figure 3. Oscillator Power Filter
3.3
Supply Voltage Sequencing
Figure 4 shows situations in sequencing the I/O VDD (EVDD), SDRAM VDD (SDVDD), PLL VDD (PVDD), and internal logic/core VDD (IVDD).
3.3V
Supplies Stable
EVDD (3.3V)
DC Power Supply Voltage
2.5V 1.8V 1.5V
SDVDD (2.5V -- DDR) SDVDD (1.8V -- DDR2) IVDD, PVDD
0 Time
Notes:
1
Input voltage must not be greater than the supply voltage (EVDD, SDVDD, IVDD, or PVDD) by more than 0.5V at any time, including during power-up. 2 Use 50 V/millisecond or slower rise time for all supplies.
Figure 4. Supply Voltage Sequencing and Separation Cautions The relationship between SDVDD and EVDD is non-critical during power-up and power-down sequences. SDVDD (2.5V or 1.8V) and EVDD are specified relative to IVDD.
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 6 Freescale Semiconductor
Pin Assignments and Reset States
3.3.1
Power-Up Sequence
If EVDD/SDVDD are powered up with the IVDD at 0 V, the sense circuits in the I/O pads cause all pad output drivers connected to the EVDD/SDVDD to be in a high impedance state. There is no limit on how long after EVDD/SDVDD powers up before IVDD must power up. The rise times on the power supplies should be slower than 50 V/millisecond to avoid turning on the internal ESD protection clamp diodes.
3.3.2
Power-Down Sequence
If IVDD/PVDD are powered down first, sense circuits in the I/O pads cause all output drivers to be in a high impedance state. There is no limit on how long after IVDD and PVDD power down before EVDD or SDVDD must power down. There are no requirements for the fall times of the power supplies.
4
4.1
Pin Assignments and Reset States
Signal Multiplexing
The following table lists all the MCF5445x pins grouped by function. The Dir column is the direction for the primary function of the pin only. Refer to Section 4, "Pin Assignments and Reset States," for package diagrams. For a more detailed discussion of the MCF5445x signals, consult the MCF54455 Reference Manual (MCF54455RM).
NOTE
In this table and throughout this document, a single signal within a group is designated without square brackets (i.e., FB_AD23), while designations for multiple signals within a group use brackets (i.e., FB_AD[23:21]) and is meant to include all signals within the two bracketed numbers when these numbers are separated by a colon.
NOTE
The primary functionality of a pin is not necessarily its default functionality. Most pins that are muxed with GPIO default to their GPIO functionality. See Table 3 for a list of the exceptions. Table 3. Special-Case Default Signal Functionality
Pin FB_AD[31:0] FB_BE/BWE[3:0] FB_CS[3:1] FB_OE FB_R/W FB_TA FB_TS 256 MAPBGA 360 TEPBGA
FB_AD[31:0] except when serial boot selects 0-bit boot port size. FB_BE/BWE[3:0] FB_CS[3:1] FB_OE FB_R/W FB_TA FB_TS
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 7
Pin Assignments and Reset States
Table 3. Special-Case Default Signal Functionality (continued)
Pin PCI_GNT[3:0] PCI_REQ[3:0] IRQ1 ATA_RESET 256 MAPBGA GPIO GPIO GPIO GPIO 360 TEPBGA PCI_GNT[3:0] PCI_REQ[3:0] PCI_INTA and configured as an agent. ATA reset
Table 4. MCF5445x Signal Information and Muxing
Voltage Domain Pull-up (U)1 Pull-down (D) MCF54452 MCF54453 MCF54454 MCF54455 360 TEPBGA Direction2
Signal Name
GPIO
Alternate 1
Alternate 2
MCF54450 MCF54451 256 MAPBGA
Reset RESET RSTOUT -- -- -- -- -- -- Clock EXTAL/PCI_CLK XTAL -- -- -- -- -- -- Mode Selection BOOTMOD[1:0] -- -- -- FlexBus FB_AD[31:24] PFBADH[7:0]4 PFBADMH[7:0]4 PFBADML[7:0]4 PFBADL[7:0]4 PBE[3:2] PBE[1:0] -- PCS[3:1] -- PFBCTL3 PFBCTL2 PFBCTL1 FB_D[31:24] -- --
I/O EVDD A14, A13, D12, C12, B12, A12, D11, C11 B11, A11, D10, C10, B10, A10, D9, C9 B9, A9, D8, C8, B8, A8, D7, C7 J2, K4, J1, K1-3, L1, L4 L2, L3, M1-4, N1-2 P1-2, R1-3, P4, T1-2
U --
I O
EVDD EVDD
L4 M15
Y18 B17
-- U3
I O
EVDD EVDD
M16 L16
A16 A17
--
I
EVDD
M5, M7
AB17, AB21
FB_AD[23:16]
FB_D[23:16]
--
--
I/O
EVDD
FB_AD[15:8] FB_AD[7:0] FB_BE/BWE[3:2] FB_BE/BWE[1:0] FB_CLK FB_CS[3:1] FB_CS0 FB_OE FB_R/W FB_TA
FB_D[15:8] FB_D[7:0] FB_TSIZ[1:0] -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- U
I/O I/O O O O O O O O I
EVDD EVDD EVDD EVDD EVDD EVDD EVDD EVDD EVDD EVDD
B7, A7, D6, C6, B6, T3-4, U1-3, V1-2, A6, D5, C5 W1 B5, A5 B4, A4 B13 C2, D4, C3 C4 A2 B2 B1 Y1, W2 W3, Y2 J3 W5, AA4, AB3 Y4 AA1 AA3 AB2
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 8 Freescale Semiconductor
Pin Assignments and Reset States
Table 4. MCF5445x Signal Information and Muxing (continued)
Voltage Domain Pull-up (U)1 Pull-down (D) MCF54452 MCF54453 MCF54454 MCF54455 360 TEPBGA
Y3
Direction2
Signal Name
GPIO
Alternate 1
Alternate 2
MCF54450 MCF54451 256 MAPBGA
FB_TS
PFBCTL0
FB_ALE
FB_TBST PCI Controller5
--
O
EVDD
A3
PCI_AD[31:24]
--
FB_A[31:24]
--
--
I/O
EVDD
--
C11, D11, A10, B10, J4, G2, G3, F1
PCI_AD[23:0]
--
FB_A[23:0]
--
--
I/O
EVDD
K14-13, J15-13, D12, C12, B12, H13-15, G15-13, A11, B11, B9, D9, F14-13, E15-13, D10, A8, B8, A5, D16, B16, C15, B5, A4, A3, B3, D4, B15, C14, D15, D3, E3-E1, F3, C2, C16, D14 D2, C1 -- -- -- -- -- -- G4, E4, D1, B1 F2 B2 B7 C8, C9 A9
PCI_CBE[3:0] PCI_DEVSEL PCI_FRAME PCI_GNT3 PCI_GNT[2:1] PCI_GNT0/ PCI_EXTREQ PCI_IDSEL PCI_IRDY PCI_PAR PCI_PERR PCI_REQ3 PCI_REQ[2:1] PCI_REQ0/ PCI_EXTGNT PCI_RST PCI_SERR PCI_STOP PCI_TRDY
-- -- -- PPCI7 PPCI[6:5] PPCI4 -- -- -- -- PPCI3 PPCI[2:1] PPCI0 -- -- -- --
-- -- -- ATA_DMACK -- -- -- -- -- -- ATA_INTRQ -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SDRAM Controller
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
I/O O I/O O O O
EVDD EVDD EVDD EVDD EVDD EVDD
I I/O I/O I/O I I I
EVDD EVDD EVDD EVDD EVDD EVDD EVDD
-- -- -- -- -- -- --
D5 C3 C4 B4 C7 D7, C5 A2
O I/O I/O I/O
EVDD EVDD EVDD EVDD
-- -- -- --
B6 A6 A7 C10
SD_A[13:0]
--
--
--
--
O
SDVDD
R1, P1, N2, P2, R2, T2, M4, N3, P3, R3, T3, T4, R4, N4 P4, T5 T6 N5
V22, U20-22, T19-22, R20-22, N19, P20-21 P22, P19 L19 N22
SD_BA[1:0] SD_CAS SD_CKE
-- -- --
-- -- --
-- -- --
-- -- --
O O O
SDVDD SDVDD SDVDD
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 9
Pin Assignments and Reset States
Table 4. MCF5445x Signal Information and Muxing (continued)
Voltage Domain Pull-up (U)1 Pull-down (D) MCF54452 MCF54453 MCF54454 MCF54455 360 TEPBGA
L22 M22 L20, M20
Direction2
Signal Name
GPIO
Alternate 1
Alternate 2
MCF54450 MCF54451 256 MAPBGA
SD_CLK SD_CLK SD_CS[1:0] SD_D[31:16]
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
O O O I/O
SDVDD SDVDD SDVDD
T9 T8 P6, R6
SDVDD N6, T7, N7, P7, R7, L21, K22, K21, R8, P8, N8, N9, K20, J20, J19, J21, T10, R10, P10, J22, H20, G22, N10, T11, R11, G21, G20, G19, P11 F22, F21, F20 SDVDD SDVDD SDVDD SDVDD SDVDD P9, N12 R9, N11 P5 M8 R5 H21, E21 H22, E22 N21 M21 N20
SD_DM[3:2] SD_DQS[3:2] SD_RAS SD_VREF SD_WE
-- -- -- -- --
-- -- -- -- --
-- -- -- -- -- External Interrupts Port6
-- -- -- -- --
O O O I O
IRQ7 IRQ4 IRQ3 IRQ1
PIRQ7 PIRQ4 PIRQ3 PIRQ1
-- -- -- PCI_INTA FEC0
-- SSI_CLKIN -- --
-- -- -- --
I I I I
EVDD EVDD EVDD EVDD
L1 L2 L3 F15
ABB13 ABB13 AB14 C6
FEC0_MDC FEC0_MDIO FEC0_COL FEC0_CRS FEC0_RXCLK FEC0_RXDV FEC0_RXD[3:2] FEC0_RXD1 FEC0_RXD0 FEC0_RXER FEC0_TXCLK FEC0_TXD[3:2] FEC0_TXD1
PFECI2C3 PFECI2C2 PFEC0H4 PFEC0H0 PFEC0H3 PFEC0H2 PFEC0L[3:2] PFEC0L1 PFEC0H1 PFEC0L0 PFEC0H7 PFEC0L[7:6] PFEC0L5
-- -- -- -- -- FEC0_RMII_ CRS_DV -- FEC0_RMII_RXD1 FEC0_RMII_RXD0 FEC0_RMII_RXER FEC0_RMII_ REF_CLK -- FEC0_RMII_TXD1
-- -- ULPI_DATA7 ULPI_DATA6 ULPI_DATA1 -- ULPI_DATA[5:4] -- -- -- -- ULPI_DATA[3:2] --
-- -- -- -- -- -- -- -- -- -- -- -- --
O I/O I I I I
EVDD EVDD EVDD EVDD EVDD EVDD
F3 F2 E1 F1 G1 G2
AB8 Y7 AB7 AA7 AA8 Y8
I I I I I
EVDD EVDD EVDD EVDD EVDD
G3, G4 H1 H2 H3 H4
AB9, Y9 W9 AB10 AA10 Y10
O O
EVDD EVDD
J1, J2 J3
W10, AB11 AA11
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 10 Freescale Semiconductor
Pin Assignments and Reset States
Table 4. MCF5445x Signal Information and Muxing (continued)
Voltage Domain Pull-up (U)1 Pull-down (D) MCF54452 MCF54453 MCF54454 MCF54455 360 TEPBGA
Y11 W11 AB12
Direction2
Signal Name
GPIO
Alternate 1
Alternate 2
MCF54450 MCF54451 256 MAPBGA
FEC0_TXD0 FEC0_TXEN FEC0_TXER
PFEC0H5 PFEC0H6 PFEC0L4
FEC0_RMII_TXD0 FEC0_RMII_TXEN --
-- -- ULPI_DATA0 FEC1
-- -- --
O O O
EVDD EVDD EVDD
J4 K1 K2
FEC1_MDC FEC1_MDIO FEC1_COL FEC1_CRS FEC1_RXCLK FEC1_RXDV FEC1_RXD[3:2] FEC1_RXD1 FEC1_RXD0 FEC1_RXER FEC1_TXCLK FEC1_TXD[3:2] FEC1_TXD1 FEC1_TXD0 FEC1_TXEN FEC1_TXER
PFECI2C5 PFECI2C4 PFEC1H4 PFEC1H0 PFEC1H3 PFEC1H2 PFEC1L[3:2] PFEC1L1 PFEC1H1 PFEC1L0 PFEC1H7 PFEC1L[7:6] PFEC1L5 PFEC1H5 PFEC1H6 PFEC1L4
-- -- -- -- -- FEC1_RMII_ CRS_DV -- FEC1_RMII_RXD1 FEC1_RMII_RXD0 FEC1_RMII_RXER FEC1_RMII_ REF_CLK -- FEC1_RMII_TXD1 FEC1_RMII_TXD0 FEC1_RMII_TXEN --
ATA_DIOR ATA_DIOW ATA_DATA7 ATA_DATA6 ATA_DATA5 ATA_DATA15 ATA_DATA[4:3] ATA_DATA14 ATA_DATA13 ATA_DATA12 ATA_DATA11 ATA_DATA[2:1] ATA_DATA10 ATA_DATA9 ATA_DATA8 ATA_DATA0 USB On-the-Go
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
O I/O I I I I
EVDD EVDD EVDD EVDD EVDD EVDD
-- -- -- -- -- --
W20 Y22 AB18 AA18 W14 AB15
I I I I I
EVDD EVDD EVDD EVDD EVDD
-- -- -- -- --
AA15, Y15 AA17 Y17 W17 AB19
O O O O O
EVDD EVDD EVDD EVDD EVDD
-- -- -- -- --
Y19, W18 AA19 Y20 AA21 AA22
USB_DM USB_DP USB_VBUS_EN USB_VBUS_OC
-- -- PUSB1 PUSB0
-- -- USB_PULLUP --
-- -- ULPI_NXT ULPI_STP ATA
-- -- -- UD7
O O O I
USB VDD USB VDD USB VDD USB VDD
F16 E16 E5 B3
A14 A15 AA2 V4
ATA_BUFFER_EN ATA_CS[1:0]
PATAH5 PATAH[4:3]
-- --
-- --
-- --
O O
EVDD EVDD
-- --
Y13 W21, W22
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 11
Pin Assignments and Reset States
Table 4. MCF5445x Signal Information and Muxing (continued)
Voltage Domain Pull-up (U)1 Pull-down (D) MCF54452 MCF54453 MCF54454 MCF54455 360 TEPBGA
V19-21 W13 AA14 Y14
Direction2
Signal Name
GPIO
Alternate 1
Alternate 2
MCF54450 MCF54451 256 MAPBGA
ATA_DA[2:0] ATA_RESET ATA_DMARQ ATA_IORDY
PATAH[2:0] PATAL2 PATAL1 PATAL0
-- -- -- --
-- -- -- -- Real Time Clock
-- -- -- --
O O I I
EVDD EVDD EVDD EVDD
-- -- -- --
EXTAL32K XTAL32K
-- --
-- -- SSI
-- --
-- --
I O
EVDD EVDD
J16 H16
A13 A12
SSI_MCLK SSI_BCLK SSI_FS SSI_RXD SSI_TXD
PSSI4 PSSI3 PSSI2 PSSI1 PSSI0
-- U1CTS U1RTS U1RXD U1TXD I2C
-- -- -- -- --
-- -- -- UD UD
O I/O I/O I O
EVDD EVDD EVDD EVDD EVDD
T13 R13 P12 T12 R12
D20 E19 E20 D21 D22
I2C_SCL I2C_SDA
PFECI2C1 PFECI2C0
-- --
U2TXD U2RXD DMA
U U
I/O I/O
EVDD EVDD
K3 K4
AA12 Y12
DACK1 DREQ1 DACK0 DREQ0
PDMA3 PDMA2 PDMA1 PDMA0
-- -- DSPI_PCS3 --
ULPI_DIR USB_CLKIN -- -- DSPI
-- U -- U
O I O I
EVDD EVDD EVDD EVDD
M14 P16 N15 N16
C17 C18 A18 B18
DSPI_PCS5/PCSS DSPI_PCS2 DSPI_PCS1 DSPI_PCS0/SS DSPI_SCK DSPI_SIN DSPI_SOUT
PDSPI6 PDSPI5 PDSPI4 PDSPI3 PDSPI2 PDSPI1 PDSPI0
-- -- SBF_CS -- SBF_CK SBF_DI SBF_DO
-- -- -- -- -- -- --
-- -- -- U --
8
O O O I/O I/O I O
EVDD EVDD EVDD EVDD EVDD EVDD EVDD
N14 L13 P14 R16 R15 P15 N13
D18 A19 B20 D17 A20 B19 C20
--
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 12 Freescale Semiconductor
Pin Assignments and Reset States
Table 4. MCF5445x Signal Information and Muxing (continued)
Voltage Domain Pull-up (U)1 Pull-down (D) MCF54452 MCF54453 MCF54454 MCF54455 360 TEPBGA Direction2
Signal Name
GPIO
Alternate 1
Alternate 2
MCF54450 MCF54451 256 MAPBGA
UARTs U1CTS U1RTS U1RXD U1TXD U0CTS U0RTS U0RXD U0TXD PUART7 PUART6 PUART5 PUART4 PUART3 PUART2 PUART1 PUART0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
I O I O I O I O EVDD EVDD EVDD EVDD EVDD EVDD EVDD EVDD -- -- -- -- M3 M2 N1 M1 V3 U4 P3 N3 Y16 AA16 AB16 W15
Note: The UART1 and UART 2 signals are multiplexed on the DMA timers and I2C pins. DMA Timers DT3IN DT2IN DT1IN DT0IN PTIMER3 PTIMER2 PTIMER1 PTIMER0 DT3OUT DT2OUT DT1OUT DT0OUT U2RXD U2TXD U2CTS U2RTS BDM/JTAG9 PSTDDATA[7:0] -- -- -- --
O EVDD E2, D1, F4, E3, D2, AA6, AB6, AB5, C1, E4, D3 W6, Y6, AA5, AB4, Y5 M11 P13 T15 T14 R14 M13 C21 C22 C19 A21 B21 B22
-- -- -- --
I I I I
EVDD EVDD EVDD EVDD
C13 D13 B14 A15
H2 H1 H3 G1
JTAG_EN PSTCLK DSI DSO BKPT DSCLK
-- -- -- -- -- --
-- TCLK TDI TDO TMS TRST Test
-- -- -- -- -- --
D -- U -- U U
I I I O I I
EVDD EVDD EVDD EVDD EVDD EVDD
TEST PLLTEST
-- --
-- --
-- --
D --
I O
EVDD EVDD
M6 K16
AB20 D15
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 13
Pin Assignments and Reset States
Table 4. MCF5445x Signal Information and Muxing (continued)
Voltage Domain Pull-up (U)1 Pull-down (D) MCF54452 MCF54453 MCF54454 MCF54455 360 TEPBGA Direction2
Signal Name
GPIO
Alternate 1
Alternate 2
MCF54450 MCF54451 256 MAPBGA
Power Supplies IVDD -- -- -- -- -- --
E6-12, F5, F12 D6, D8, D14, F4, H4, N4, R4, W4, W7, W8, W12, W16, W19
EVDD
--
--
--
--
--
--
G5, G12, H5, H12, D13, D19, G8, J5, J12, K5, K12, G11, G14, G16, J7, L5-6, L12 J16, L7, L16, N16, P7, R16, T8, T12, T14, T16 L7-11, M9, M10 L14 K15 M12 F19, H19, K19, M19, R19, U19 B16 C14 C13
SD_VDD VDD_OSC VDD_A_PLL VDD_RTC VSS
-- -- -- -- --
-- -- -- -- --
-- -- -- -- --
-- -- -- -- --
-- -- -- -- --
-- -- -- -- --
A1, A16, F6-11, A1, A22, B14, G7, G6-11, H6-11, G9-10, G12-13, J6-11, K6-11, T1, G15, H7, H16, T16 J9-14, K7, K9-14, K16, L9-14, M7, M9-M14, M16, N9-14, P9-14, P16, R7, T7, T9-11, T13, T15, AB1, AB22 L15 C16
VSS_OSC
1 2 3 4 5
--
--
--
--
--
--
6 7 8 9
Pull-ups are generally only enabled on pins with their primary function, except as noted. Refers to pin's primary function. Enabled only in oscillator bypass mode (internal crystal oscillator is disabled). Serial boot must select 0-bit boot port size to enable the GPIO mode on these pins. When the PCI is enabled, all PCI bus pins come up configured as such. This includes the PCI_GNT and PCI_REQ lines, which have GPIO. The IRQ1/PCI_INTA signal is a special case. It comes up as PCI_INTA when booting as a PCI agent and as GPIO when booting as a PCI host. For the 360 TEPBGA, booting with PCI disabled results in all dedicated PCI pins being safe-stated. The PCI_GNT and PCI_REQ lines and IRQ1/PCI_INTA come up as GPIO. GPIO functionality is determined by the edge port module. The pin multiplexing and control module is only responsible for assigning the alternate functions. Depends on programmed polarity of the USB_VBUS_OC signal. Pull-up when the serial boot facility (SBF) controls the pin If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The pin multiplexing and control module is not responsible for assigning these pins.
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 14 Freescale Semiconductor
Pin Assignments and Reset States
4.2
1 A VSS
Pinout--256 MAPBGA
2 FB_OE 3 FB_TS 4 5 6 FB_AD 2 FB_AD 3 FB_AD 4 FB_AD 5 IVDD 7 FB_AD 6 FB_AD 7 FB_AD 8 FB_AD 9 IVDD 8 FB_AD 10 FB_AD 11 FB_AD 12 FB_AD 13 IVDD 9 FB_AD 14 FB_AD 15 FB_AD 16 FB_AD 17 IVDD 10 FB_AD 18 FB_AD 19 FB_AD 20 FB_AD 21 IVDD 11 FB_AD 22 FB_AD 23 FB_AD 24 FB_AD 25 IVDD 12 FB_AD 26 FB_AD 27 FB_AD 28 FB_AD 29 IVDD 13 FB_AD 30 FB_CLK 14 FB_AD 31 T1IN 15 T0IN 16 VSS A
The pinout for the MCF54450 and MCF54451 packages are shown below.
FB_BE/ FB_BE/ BWE0 BWE2 FB_BE/ FB_BE/ BWE1 BWE3
B
FB_TA
USB_ FB_R/W VBUS_ OC
PCI_AD PCI_AD B 4 6
C D
PST FB_AD FB_CS3 FB_CS1 FB_CS0 DDATA2 0 PST PST PST FB_AD FB_CS2 DDATA6 DDATA3 DDATA0 1 FEC0_ COL FEC0_ CRS FEC0_ RXCLK FEC0_ RXD1 FEC0_ TXD3 FEC0_ TXEN IRQ_7 USB_ PST PST PST VBUS_ DDATA7 DDATA4 DDATA1 EN FEC0_ MDIO FEC0_ RXDV FEC0_ RXD0 FEC0_ TXD2 FEC0_ TXER IRQ_4 U0RTS FEC0_ MDC FEC0_ RXD3 FEC0_ RXER FEC0_ TXD1 I2C_ SCL IRQ_3 U0CTS PST DDATA5 FEC0_ RXD2 FEC0_ TXCLK FEC0_ TXD0 I2C_ SDA RESET SD_A7 SD_A0 IVDD EVDD EVDD EVDD EVDD EVDD BOOT MOD1 SD_ CKE SD_ RAS SD_WE
T3IN T2IN
PCI_AD PCI_AD PCI_AD C 3 5 1 PCI_AD PCI_AD PCI_AD D 0 2 7 USB_ DP USB_ DM NC XTAL 32K EXTAL 32K PLL TEST XTAL E
E
PCI_AD PCI_AD PCI_AD 8 9 10 PCI_AD PCI_AD 11 12 IRQ_1
F G H J K L
VSS VSS VSS VSS VSS EVDD TEST
VSS VSS VSS VSS VSS SDVDD BOOT MOD0
VSS VSS VSS VSS VSS SDVDD SD_ VREF
VSS VSS VSS VSS VSS SDVDD SDVDD
VSS VSS VSS VSS VSS SDVDD SDVDD
VSS VSS VSS VSS VSS SDVDD JTAG_ EN SD_ DQS2
IVDD EVDD EVDD EVDD EVDD EVDD VDD_ RTC SD_DM2 SSI_FS
F G H J K L
PCI_AD PCI_AD PCI_AD 13 14 15 PCI_AD PCI_AD PCI_AD 18 17 16 PCI_AD PCI_AD PCI_AD 19 20 21 PCI_AD PCI_AD VDD_A 22 23 _PLL DSPI_ PCS2 TRST DSPI_ SOUT TCLK SSI_ BCLK SSI_ MCLK 13 VDD_ OSC DACK1 DSPI_ PCS5 DSPI_ PCS1 TMS TDO 14 VSS_ OSC RST OUT DACK0 DSPI_ SIN DSPI_ SCK TDI 15
M U0TXD
EXTAL M DREQ0 N DREQ1 P DSPI_ PCS0 VSS 16 R T
N U0RXD SD_A11 SD_A6
SD_D31 SD_D29 SD_D24 SD_D23 SD_D19 SD_ CS1 SD_ CS0 SD_ CAS 6 SD_D28 SD_D25 SD_D27 SD_D26 SD_D30 7 SD_ CLK 8 SD_ DM3 SD_ DQS3 SD_ CLK 9
P SD_A12 SD_A10 SD_A5 SD_BA1 R SD_A13 SD_A9 T VSS 1 SD_A8 2 SD_A4 SD_A3 3 SD_A1
SD_D20 SD_D16
SD_D21 SD_D17 SSI_TXD SD_D22 SD_D18 SSI_RXD 10 11 12
SD_A2 SD_BA0 4 5
Figure 5. MCF54450 and MCF54451 Pinout (256 MAPBGA)
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 15
Pin Assignments and Reset States
4.3
1 A GND PCI_ CBE0 PCI_ AD0 PCI_ CBE1 PCI_ AD4 PCI_ AD24 T0IN 2 PCI_ REQ0 PCI_ FRAME PCI_ AD2 PCI_ AD1 PCI_ AD5 PCI_DE VSEL PCI_ AD26 T3IN FB_AD 31 FB_AD 27 FB_AD 23 FB_AD 20 FB_AD 16 FB_AD 14 FB_AD 12 FB_AD 8 FB_AD 4 FB_AD 1 FB_BE/ BWE2 FB_BE/ BWE0 USB_ VBUS_ EN FB_TA 2
Pinout--360 TEPBGA
3 PCI_ AD10 PCI_ AD9 PCI_ IRDY PCI_ AD7 PCI_ AD6 PCI_ AD3 PCI_ AD25 T1IN 4 PCI_ AD11 PCI_ PERR PCI_ PAR PCI_ AD8 PCI_ CBE2 IVDD PCI_ CBE3 IVDD PCI_ AD27 FB_AD 30 FB_AD 24 FB_AD 18 IVDD FB_AD 10 IVDD FB_AD 6 U1RTS USB_ VBUS_ OC IVDD FB_CS3 PST DDATA4 IVDD IVDD FEC0_ RXD1 FEC0_ RXD2 FEC0_ TXD3 FEC0_ TXCLK FEC0_ TXEN FEC0_ TXD0 IVDD ATA_ RESET ATA_BU FFER_ EN FEC1_ RXCLK ATA_ IORDY U0TXD IVDD FEC1_ RXER FEC1_ RXD0 FEC1_ TXD2 5 PCI_ AD13 PCI_ AD12 PCI_ REQ1 PCI_ IDSEL 6 PCI_ SERR PCI_ RST IRQ1 7 PCI_ STOP PCI_ GNT3 PCI_ REQ3 PCI_ REQ2 8 PCI_ AD15 PCI_ AD14 PCI_ GNT2 IVDD 9 PCI_ GNT0 PCI_ AD18 PCI_ GNT1 PCI_ AD17 10 PCI_ AD29 PCI_ AD28 PCI_ TRDY PCI_ AD16 11 PCI_ AD20 PCI_ AD19 PCI_ AD31 PCI_ AD30 12 XTAL 32K PCI_ AD21 PCI_ AD22 PCI_ AD23 13 EXTAL 32K NC VDD_ RTC EVDD 14 USB_ DM GND VDD_ A_PLL IVDD 15 USB_ DP NC 16 EXTAL VDD_ OSC VSS_ OSC NC 17 XTAL RST OUT DACK1 DSPI_ PCS0 18 DACK0 19 DSPI_ PCS2 DSPI_ SIN TDI 20 DSPI_ SCK DSPI_ PCS1 DSPI_ SOUT SSI_ MCLK SSI_FS 21 TDO 22 GND A
The pinout for the MCF54452, MCF54453, MCF54454, and MCF54455 packages are shown below.
B
DREQ0
TMS JTAG_ EN SSI_ RXD SD_ DM2
TRST
B
C
NC PLL TEST
DREQ1 DSPI_ PCS5
TCLK SSI_ TXD SD_ DQS2
C
D
IVDD
EVDD SSI_ BCLK SDVDD
D
E
E
F
SD_D16 SD_D17 SD_D18
F
G
GND
EVDD
GND
GND
EVDD
GND
GND
EVDD
GND
EVDD
SD_D19 SD_D20 SD_D21 SD_D22 SD_ DM3 SD_ DQS3
G
H
T2IN FB_AD 29 FB_AD 28 FB_AD 25 FB_AD 21 FB_AD 17 FB_AD 15 FB_AD 13 FB_AD 9 FB_AD 5 FB_AD 2 FB_AD 0 FB_BE/ BWE3
GND
GND
SDVDD
SD_D23
H
J
FB_CLK FB_AD 26 FB_AD 22 FB_AD 19 U1TXD
EVDD
GND
GND
GND
GND
GND
GND
EVDD
SD_D26 SD_D27 SD_D25 SD_D24
J
K
GND
GND
GND
GND
GND
GND
GND
GND
SDVDD SD_ CAS SDVDD
SD_D28 SD_D29 SD_D30 SD_ CS1 SD_ CS0 SD_WE SD_ CLK SD_ CLK SD_ CKE SD_ BA1 SD_A3
K
L
EVDD
GND
GND
GND
GND
GND
GND
EVDD
SD_D31 SD_ VREF SD_ RAS SD_A0
L
M
GND
GND
GND
GND
GND
GND
GND
GND
M
N
GND
GND
GND
GND
GND
GND
GND
EVDD
SD_A2 SD_ BA0 SDVDD
N
P
U1RXD FB_AD 11 FB_AD 7 FB_AD 3
EVDD
GND
GND
GND
GND
GND
GND
GND
SD_A1
P
R
GND
EVDD
SD_A5
SD_A4
R
T
GND
EVDD
GND
GND
GND
EVDD
GND
EVDD
GND
EVDD
SD_A9
SD_A8
SD_A7
SD_A6
T
U
SDVDD
SD_A12 SD_A11 SD_A10
U
V
U1CTS
ATA_ DA2
ATA_ DA1 FEC1_ MDC FEC1_ TXD0
ATA_ DA0 ATA_ CS1
SD_A13
V
W
FB_BE/ BWE1
IVDD
ATA_ CS0 FEC1_ MDIO
W
Y
FB_TS
FB_CS0
PST PST DDATA0 DDATA3
FEC0_ MDIO
FEC0_ RXDV
I2C_ SDA
FEC1_ RXD2
U0CTS
RESET
FEC1_ TXD3
NC
Y
AA
FB_OE
FB_R/W FB_CS2
PST PST DDATA2 DDATA7
FEC0_ CRS FEC0_ COL 7
FEC0_ RXCLK FEC0_ MDC 8
NC
FEC0_ RXER FEC0_ RXD0 10
FEC0_ TXD1 FEC0_ TXD2 11
I2C_ SCL FEC0_ TXER 12
IRQ4
ATA_ DMARQ
FEC1_ RXD3 FEC1_ RXDV 15
U0RTS
FEC1_ RXD1 BOOT MOD1 17
FEC1_ CRS FEC1_ COL 18
FEC1_ TXD1 FEC1_ TXCLK 19
NC
FEC1_ TXEN BOOT MOD0 21
FEC1_ TXER
AA
AB
GND 1
FB_CS1 3
PST PST PST DDATA1 DDATA5 DDATA6 4 5 6
FEC0_ RXD3 9
IRQ7 13
IRQ3 14
U0RXD 16
TEST 20
GND 22
AB
Figure 6. MCF54452, MCF54453, MCF54454, and MCF54455 Pinout (360 TEPBGA)
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 16 Freescale Semiconductor
Electrical Characteristics
5
Electrical Characteristics
This document contains electrical specification tables and reference timing diagrams for the MCF54455 microprocessor. This section contains detailed information on DC/AC electrical characteristics and AC timing specifications. The electrical specifications are preliminary and from previous designs or design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. However, for production silicon, these specifications will be met. Finalized specifications will be published after complete characterization and device qualifications have been completed.
NOTE
The parameters specified in this MCU document supersede any values found in the module specifications.
5.1
Absolute Maximum Ratings
Table 5. Absolute Maximum Ratings1, 2
Rating Symbol EVDD OSCVDD RTCVDD IVDD SDVDD PVDD VIN IDD TA (TL - TH) Tstg Pin Name EVDD VDD_OSC VDD_RTC IVDD SD_VDD VDD_A_PLL -- -- -- -- Value -0.3 to +4.0 -0.3 to +4.0 -0.5 to +2.0 -0.5 to +2.0 -0.3 to +4.0 -0.5 to +2.0 -0.3 to +3.6 25 -40 to +85 -55 to +150 Units V V V V V V V mA C C
External I/O pad supply voltage Internal oscillator supply voltage Real-time clock supply voltage Internal logic supply voltage SDRAM I/O pad supply voltage PLL supply voltage Digital input voltage3 Instantaneous maximum current Single pin limit (applies to all pins) 3, 4, 5 Operating temperature range (packaged) Storage temperature range
1
2
3 4 5
Functional operating conditions are given in Table 8. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Continued operation at these levels may affect device reliability or cause permanent damage to the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields. However, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., VSS or EVDD). Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, and then use the larger of the two values. All functional non-supply pins are internally clamped to VSS and EVDD. Power supply must maintain regulation within operating EVDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > EVDD) is greater than IDD, the injection current may flow out of EVDD and could result in external power supply going out of regulation. Ensure the external EVDD load shunts current greater than maximum injection current. This is the greatest risk when the MPU is not consuming power (ex; no clock). The power supply must maintain regulation within operating EVDD range during instantaneous and operating maximum current conditions.
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 17
Electrical Characteristics
5.2
Thermal Characteristics
Table 6. Thermal Characteristics
Characteristic Junction to ambient, natural convection Junction to ambient (@200 ft/min) Junction to board Junction to case Junction to top of package Maximum operating junction temperature
1
Symbol Four layer board (2s2p) Four layer board (2s2p) JA JMA JB JC jt Tj
256 MAPBGA 291,2 251,2 183 104 2
1,5
360 TEPBGA 241,2 211,2 153 114 2
1,5
Unit C/W C/W C/W C/W C/W
o
105
105
C
2 3 4 5
JMA and jt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale recommends the use of JmA and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature specification can be verified by physical measurement in the customer's system using the jt parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2. Per JEDEC JESD51-6 with the board horizontal. Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written in conformance with Psi-JT.
The average chip-junction temperature (TJ) in C can be obtained from:
T J = T A + ( P D x JMA )
Eqn. 1
Where:
TA QJMA PD PINT PI/O = = = = = Ambient Temperature, C Package Thermal Resistance, Junction-to-Ambient, C/W PINT + PI/O IDD x IVDD, Watts - Chip Internal Power Power Dissipation on Input and Output Pins -- User Determined
For most applications PI/O < PINT and can be ignored. An approximate relationship between PD and TJ (if PI/O is neglected) is:
K P D = -------------------------------( T J + 273C )
Eqn. 2
Solving equations 1 and 2 for K gives: K = P D x ( T A x 273C ) + Q JMA x P D
2
Eqn. 3
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 18 Freescale Semiconductor
Electrical Characteristics
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively for any value of TA.
5.3
ESD Protection
Table 7. ESD Protection Characteristics1, 2
Characteristics ESD Target for Human Body Model
1
Symbol HBM
Value 2000
Units V
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2 A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing is performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification.
5.4
DC Electrical Specifications
Table 8. DC Electrical Specifications
Characteristic Symbol IVDD PVDD EVDD OSCVDD RTCVDD SDVDD SDVDD SDVDD SDVREF VIH VIL VHYS Iin IOZ VOH VOL Min 1.35 1.35 3.0 3.0 1.35 2.25 1.7 1.7 Max 1.65 1.65 3.6 3.6 1.65 2.75 1.9 1.9 Units V V V V V V V V V V V mV A A V V
Internal logic supply
voltage1
PLL analog operation voltage range 1 External I/O pad supply voltage Internal oscillator supply voltage Real-time clock supply voltage SDRAM I/O pad supply voltage -- DDR mode SDRAM I/O pad supply voltage -- DDR2 mode SDRAM I/O pad supply voltage -- Mobile DDR mode SDRAM input reference voltage Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current Vin = VDD or VSS, Input-only pins High Impedance (Off-State) Leakage Current2 Vin = VDD or VSS, All input/output and output pins Output High Voltage (All input/output and all output pins) IOH = -5.0 mA Output Low Voltage (All input/output and all output pins) IOL = 5.0mA
0.49 x SDVDD 0.51 x SDVDD 0.7 x EVDD VSS - 0.3 0.06 x EVDD -1.0 -10.0 0.85 x EVDD __ 3.65 0.35 x EVDD -- 1.0 10.0 __ 0.15 x EVDD
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 19
Electrical Characteristics
Table 8. DC Electrical Specifications
Characteristic Weak Internal Pull Up Device Current, tested at VIL Max.3 Input Capacitance All input-only pins All input/output (three-state) pins Load Capacitance Low drive strength High drive strength DC Injection Current 3, 5, 6, 7 VNEGCLAMP =VSS- 0.3 V, VPOSCLAMP = VDD + 0.3 Single Pin Limit Total MCU Limit, Includes sum of all stressed pins
1 4
Symbol IAPU Cin
Min -10 -- --
Max -130 7 7
Units A pF
pF CL IIC -1.0 -10 1.0 10 25 50 mA
2 3 4 5 6 7
IVDD and PVDD should be at the same voltage. PVDD should have a filtered input. Please see the PLL section of this specification for an example circuit. There are three PVDD inputs, one for each PLL. A filter circuit should used on each PVDD input. Worst-case tristate leakage current with only one I/O pin high. Since all I/Os share power when high, the leakage current is distributed among them. With all I/Os high, this spec reduces to 2 A min/max. Refer to the MCF54455 Reference Manual signals description chapter for pins having weak internal pull-up devices. This parameter is characterized before qualification rather than 100% tested. All functional non-supply pins are internally clamped to VSS and their respective VDD. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure the external VDD load shunts current greater than the maximum injection current. This is the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low which would reduce overall power consumption. Also, at power-up, the system clock is not present during the power-up sequence until the PLL has attained lock.
5.5
ClockTiming Specifications
The clock module configures the device for one of several clocking methods. Clocking modes include internal phase-locked loop (PLL) clocking with an external clock reference or an external crystal reference supported by an internal crystal amplifier. The PLL can also be disabled, and an external oscillator can directly clock the device. The specifications in Table 9 are for the CLKIN input pin (EXTAL input driven by an external clock reference). The duty cycle specification is based on an acceptable tolerance for the PLL, which yields 50% duty-cycle internal clocks to all on-chip peripherals. The MCF5445x devices use the input clock signal as its synchronous bus clock for PCI. A poor duty cycle on the input clock, may affect the overall timing margin to external devices. If negative edge logic is used to interface to PCI, providing a 50% duty-cycle input clock aids in simplifying overall system design. Table 9. Input Clock Timing Requirements
Item C1 Cycle time Specification Min 15 Max 40 Unit ns
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 20 Freescale Semiconductor
Electrical Characteristics
Table 9. Input Clock Timing Requirements (continued)
Item 1 / C1 Frequency C2 C3 C4 Rise time (20% of vdd to 80% of vdd) Fall time (80% of vdd to 20% of vdd) Duty cycle (at 50% of vdd) Specification Min 25 40 Max 66.66 2 2 60 Unit MHz ns ns %
C1
Input Clock (CLKIN) C4 C4 C3 C2
Figure 7. Input Clock Timing Diagram Table 10. PLL Electrical Characteristics
Num 1 Characteristic PLL Reference Frequency Range Crystal reference External reference Core/System Frequency Core/System Clock Period 19 3 4 VCO Frequency (fvco = fref x PFDR) Crystal Start-up Time
2, 3
Symbol
Min. Value 16 16 512 Hz1 -- 300 -- VXTAL + 0.4 EVDD/2 + 0.4 -- -- 1
Max. Value 40 66.66 266.67 MHz 1/fsys 540 10 -- -- VXTAL - 0.4 EVDD/2 - 0.4 2 50000 60 3 1.5 1.5
Unit
fref_crystal fref_ext fsys tsys fvco tcst VIHEXT VIHEXT VILEXT VILEXT
MHz MHz -- ns MHz ms V V V V ns CLKIN % mA pF pF
2
EXTAL Input High Voltage Crystal Mode4 All other modes (External, Limp) EXTAL Input Low Voltage Crystal Mode4 All other modes (External, Limp) EXTAL Input Rise & Fall Time (20% to 80% EVDD) (External, Limp) PLL Lock Time 3, 5 Duty Cycle of XTAL Current Total on-chip stray capacitance on XTAL Total on-chip stray capacitance on EXTAL reference 3 (External, Limp)
5
6 7 8 9 10 11
tlpll tdc IXTAL CS_XTAL CS_EXTAL
-- 40 1 -- --
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 21
Electrical Characteristics
Table 10. PLL Electrical Characteristics (continued)
Num 12 13 Characteristic Crystal capacitive load Discrete load capacitance for XTAL Discrete load capacitance for EXTAL Symbol CL CL_XTAL CL_EXTAL Min. Value Max. Value Unit
See crystal spec -- 2 x (CL CS_XTAL CS_EXTAL CS_PCB)6 4.0 2.0 10 TBD pF
14 15 17
Frequency un-LOCK Range Frequency LOCK Range CLKOUT Period Jitter, Measured at fSYS Max Peak-to-peak Jitter (Clock edge to clock edge) Long Term Jitter
3, 4, 7
fUL fLCK Cjitter
-4.0 -2.0 -- --
% fsys % fsys % FB_CLK % FB_CLK
1 2 3 4 5 6 7
The minimum system frequency is the minimum input clock divided by the maximum low-power divider (16 MHz / 32,768). When the PLL is enabled, the minimum system frequency (fsys) is 150 MHz. This parameter is guaranteed by characterization before qualification rather than 100% tested. Applies to external clock reference only. Proper PC board layout procedures must be followed to achieve specifications. This parameter is guaranteed by design rather than 100% tested. This specification is the PLL lock time only and does not include oscillator start-up time. CS_PCB is the measured PCB stray capacitance on EXTAL and XTAL. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via PLL VDD, EVDD, and VSS and variation in crystal oscillator frequency increase the Cjitter percentage for a given interval.
5.6
Reset Timing Specifications
Table 11 lists specifications for the reset timing parameters shown in Figure 8. Table 11. Reset and Configuration Override Timing
Num R11 R2 R3 R4 R5 R6 R7 R8
1
Characteristic RESET valid to CLKIN (setup) CLKIN to RESET invalid (hold) RESET valid time2
Min 9 1.5 5 -- 0 20 0 --
Max -- -- -- 10 -- -- -- 1
Unit ns ns CLKIN cycles ns ns CLKIN cycles ns CLKIN cycles
CLKIN to RSTOUT valid RSTOUT valid to Configuration Override inputs valid Configuration Override inputs valid to RSTOUT invalid (setup) Configuration Override inputs invalid after RSTOUT invalid (hold) RSTOUT invalid to Configuration Override inputs High Impedance
RESET and Configuration Override data lines are synchronized internally. Setup and hold times must be met only if recognition on a particular clock is required. 2 During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously to the system. Thus, RESET must be held a minimum of 100 ns.
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 22 Freescale Semiconductor
Electrical Characteristics
CLKIN
R1 R3
RESET
R2
R4
RSTOUT
R4 R8 R5 R6 R7
Configuration Overrides*: (BOOTMOD[1:0], Override pins])
Figure 8. RESET and Configuration Override Timing
5.7
FlexBus Timing Specifications
A multi-function external bus interface called FlexBus is provided with basic functionality to interface to slave-only devices up to a maximum bus frequency of 66MHz. It can be directly connected to asynchronous or synchronous devices such as external boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional circuitry. For asynchronous devices, a simple chip-select based interface can be used. All processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be the same as the internal system bus frequency or an integer divider of that frequency. The following timing numbers indicate when data is latched or driven onto the external bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be derived from these values. Table 12. FlexBus AC Timing Specifications
Num Characteristic Frequency of Operation FB1 FB2 FB3 FB4 FB5
1
Min 25 15 -- 1.0 3.0 0
Max 66.66 40 7.0 -- -- --
Unit MHz ns ns ns ns ns
Notes
Clock Period Output Valid Output Hold Input Setup Input Hold
1
1
2
2
Specification is valid for all FB_AD[31:0], FB_BS[3:0], FB_CS[3:0], FB_OE, FB_R/W, FB_TBST, FB_TSIZ[1:0], and FB_TS. 2 Specification is valid for all FB_AD[31:0] and FB_TA.
NOTE The processor drives the data lines during the first clock cycle of the transfer with the full 32-bit address. This may be ignored by standard connected devices using non-multiplexed address and data buses. However, some applications may find this feature beneficial. The address and data busses are muxed between the FlexBus and PCI controller. At the end of the read and write bus cycles the address signals are indeterminate.
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 23
Electrical Characteristics
S0 S1 S2 S3
FB_CLK
FB1 FB3 ADDR[Y:0] FB2 FB5 DATA FB4
FB_AD[Y:0] Mux'd Bus FB_AD[31:X]
ADDR[31:X]
FB_A[31:0] Non-Mux'd Bus FB_D[31:X] FB_R/W FB_ALE FB_CSn, FB_OE, FB_BE/BWEn
FB4 ADDR[31:X]
ADDR[31:0]
DATA
FB5
FB_TA FB_TSIZ[1:0] TSIZ[1:0]
Figure 9. FlexBus Read Timing
S0 S1 S2 S3
FB_CLK
FB1 FB3 ADDR[Y:0] FB2
FB_AD[Y:0] Mux'd Bus FB_AD[31:X] FB_A[31:0] Non-Mux'd Bus FB_D[31:X] FB_R/W FB_ALE FB_CSn, FB_BE/BWEn FB_OE FB_TA FB_TSIZ[1:0]
FB4 ADDR[31:X]
ADDR[31:X] ADDR[31:0]
DATA
DATA
FB5
TSIZ[1:0]
Figure 10. Flexbus Write Timing
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 24 Freescale Semiconductor
Electrical Characteristics
5.8
SDRAM AC Timing Characteristics
The following timing numbers must be followed to properly latch or drive data onto the SDRAM memory bus. All timing numbers are relative to the four DQS byte lanes. Table 13. SDRAM Timing Specifications
Num Characteristic Frequency of Operation DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 Clock Period Pulse Width High Pulse Width Low Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_CS[1:0] -- Output Valid Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_CS[1:0] -- Output Hold Write Command to first DQS Latching Transition Data and Data Mask Output Setup (DQ-->DQS) Relative to DQS (DDR Write Mode) Data and Data Mask Output Hold (DQS-->DQ) Relative to DQS (DDR Write Mode) Input Data Skew Relative to DQS (Input Setup) tSDCK tSDCKH tSDCKL tCMV tCMH tDQSS tQS tQH tIS tIH Symbol Min 60 7.5 0.45 0.45 -- 2.0 (1.0 x tSDCK) - 0.6ns 1.0 1.0 -- (0.25 x tSDCK) + 0.5ns Max 133.33 16.67 0.55 0.55 (0.5 x tSDCK) + 1.0ns -- (1.0 x tSDCK) + 0.6ns -- -- 1.0 -- Unit MHz ns tSDCK tSDCK ns ns ns ns ns ns ns
4 5 6 2
Notes
1
3
3
7 8
DD10 Input Data Hold Relative to DQS.
1 2 3 4
5 6 7 8
The SDRAM interface operates at the same frequency as the internal system bus. Pulse width high plus pulse width low cannot exceed min and max clock period. Command output valid should be 1/2 the memory bus clock (tSDCK) plus some minor adjustments for process, temperature, and voltage variations. This specification relates to the required input setup time of DDR memories. The microprocessor's output setup should be larger than the input setup of the DDR memories. If it is not larger, then the input setup on the memory is in violation. SD_D[31:24] is relative to SD_DQS[3]; SD_D[23:16] is relative to SD_DQS[2] The first data beat is valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats are valid for each subsequent DQS edge. This specification relates to the required hold time of DDR memories. SD_D[31:24] is relative to SD_DQS[3]; SD_D[23:16] is relative to SD_DQS[2] Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other factors). Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line becomes invalid.
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 25
Electrical Characteristics
DD1
DD2
SD_CLK
DD3
SD_CLK
DD5
SD_CSn,SD_WE, SD_RAS, SD_CAS
DD4
CMD DD6 ROW COL DD7
SD_A[13:0]
SD_DM3/SD_DM2
DD8
SD_DQS3/SD_DQS2
DD7
SD_D[31:24]/SD_D[23:16]
WD1 WD2 WD3 WD4 DD8
Figure 11. DDR Write Timing
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 26 Freescale Semiconductor
Electrical Characteristics
DD1 SD_CLK
DD2
DD3 SD_CLK
DD5 SD_CSn,SD_WE, SD_RAS, SD_CAS DD4 SD_A[13:0] ROW COL CMD
CL=2
CL=2.5
DD9 SD_DQS3/SD_DQS2 CL = 2 DQS Read Preamble DD10 D[31:24]/D[23:16]
DQS Read Postamble
SD_DQS3/SD_DQS2 CL = 2.5
WD1 WD2 WD3 WD4 DQS Read DQS Read Preamble Postamble
D[31:24]/D[23:16] WD1 WD2 WD3 WD4
Figure 12. DDR Read Timing
5.9
PCI Bus Timing Specifications
Table 14. PCI Timing Specifications1,2
33 MHz3 66 MHz3 Min 33.33 15 3.0 5.0 0 -- Max 66.66 30 -- -- -- 6.0 Unit MHz ns ns ns ns ns
The PCI bus on the device is PCI 2.2 compliant. The following timing numbers are mostly from the PCI 2.2 spec. Refer to the PCI 2.2 spec for a more detailed timing analysis.
Num Frequency of Operation P1 P2 P3 P4 P5 Clock Period
Characteristic Min -- 30 7.0 10.0 0 -- Max 33.33 -- -- -- -- 11.0
Bused PCI signals -- input setup PCI_GNT[3:0]/PCI_REQ[3:0] -- input setup All PCI signals -- input hold Bused PCI signals -- output valid
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 27
Electrical Characteristics
Table 14. PCI Timing Specifications1,2 (continued)
33 MHz3 Num P6 P7
1 2
66 MHz3 Min -- 1.0 Max 6.0 -- Unit ns ns
Characteristic Min PCI_REQ[3:0]/PCI_GNT[3:0] -- output valid All PCI signals -- output hold -- 2.0 Max 12.0 --
The PCI bus operates at the CLKIN frequency. All timings are relative to the input clock, CLKIN. All PCI signals are bused signals except for PCI_GNT[3:0] and PCI_REQ[3:0]. These signals are defined as point-to-point signals by the PCI Specification. 3 The 66-MHz parameters are only guaranteed when the 66-MHz PCI pad slew rates are selected. Likewise, the 33-MHz parameters are only guaranteed when the 33-MHz PCI pad slew rates are selected.
P1
CLKIN
P5 P6 P7
Output Valid/Hold
Output Valid P2 P3
P4 Input Valid
Input Setup/Hold
Figure 13. PCI Timing
5.9.1
Overshoot and Undershoot
Figure 14 shows the specification limits for overshoot and undershoot for PCI I/O. To guarantee long term reliability, the specification limits shown must be followed. Good transmission line design practices should be observed to guarantee the specification limits.
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 28 Freescale Semiconductor
Electrical Characteristics
VDD + 0.9V VDD + 0.5V VDD
GND GND - 0.5V GND - 1.0V Not to exceed 17% of PCI Cycle
Figure 14. Overshoot and Undershoot Limits
5.10
ULPI Timing Specifications
The ULPI interface is fully compliant with the industry standard UTMI+ Low Pin Interface. Control and data timing requirements for the ULPI pins are given in Table 15. These timings apply to synchronous mode only. All timings are measured with respect to the clock as seen at the USB_CLKIN pin on the MCF5445x. The ULPI PHY is the source of the 60MHz clock.
NOTE
The USB controller requires a 60-MHz clock, even if using the on-chip FS/LS transceiver instead of the ULPI interface. In this case, the 60-MHz clock can be generated by the PLL or input on the USB_CLKIN pin. Table 15. ULPI Interface Timing
Num Characteristic USB_CLKIN operating frequency USB_CLKIN duty cycle U1 U2 U3 U4 U5 USB_CLKIN clock period Input Setup (control and data) Input Hold (control and data) Output Valid (control and data) Output Hold (control and data) Min -- -- -- 5.0 1.0 -- 1.0 Nominal 60 50 16.67 -- -- -- -- Max -- -- -- -- -- 9.5 -- Units MHz % ns ns ns ns
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 29
Electrical Characteristics
U1
USB_CLKIN
U2 U3
ULPI_DIR / ULPI_NXT (Control Input)
U2 U3
ULPI_DATA[7:0] (Data Input)
U4 U5
ULPI_STP (Control Output)
U4 U5
ULPI_DATA[7:0] (Data Output)
Figure 15. ULPI Timing Diagram
5.11
SSI Timing Specifications
This section provides the AC timings for the SSI in master (clocks driven) and slave modes (clocks input). All timings are given for non-inverted serial clock polarity (SSI_TCR[TSCKP] = 0, SSI_RCR[RSCKP] = 0) and a non-inverted frame sync (SSI_TCR[TFSI] = 0, SSI_RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal (SSI_BCLK) and/or the frame sync (SSI_FS) shown in the figures below. Table 16. SSI Timing -- Master Modes1
Num S1 S2 S3 S4 S5 S6 S7 S8 S9 S10
1 2
Description SSI_MCLK cycle time SSI_MCLK pulse width high / low SSI_BCLK cycle time SSI_BCLK pulse width SSI_BCLK to SSI_FS output valid SSI_BCLK to SSI_FS output invalid SSI_BCLK to SSI_TXD valid SSI_BCLK to SSI_TXD invalid / high impedence SSI_RXD / SSI_FS input setup before SSI_BCLK SSI_RXD / SSI_FS input hold after SSI_BCLK
Symbol tMCLK
Min 2 x tSYS 45% 8 x tSYS 45% -- 0 -- -2 10 0
Max -- 55% -- 55% 15 -- 15 -- -- --
Units ns tMCLK ns tBCLK ns ns ns ns ns ns
Notes
2
tBCLK
3
All timings specified with a capactive load of 25pF. SSI_MCLK can be generated from SSI_CLKIN or a divided version of the internal system clock (fsys). 3 SSI_BCLK can be derived from SSI_CLKIN or a divided version of the internal system clock (f ). sys
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 30 Freescale Semiconductor
Electrical Characteristics
Table 17. SSI Timing -- Slave Modes1
Num S11 S12 S13 S14 S15 S16 S17 S18
1
Description SSI_BCLK cycle time SSI_BCLK pulse width high / low SSI_FS input setup before SSI_BCLK SSI_FS input hold after SSI_BCLK SSI_BCLK to SSI_TXD / SSI_FS output valid SSI_BCLK to SSI_TXD / SSI_FS output invalid / high impedence SSI_RXD setup before SSI_BCLK SSI_RXD hold after SSI_BCLK
Symbol tBCLK
Min 8 x tSYS 45% 10 2 -- 0 10 2
Max -- 55% -- -- 15 -- -- --
Units ns tBCLK ns ns ns ns ns ns
Notes
All timings specified with a capactive load of 25pF.
S1
S2
S2
SSI_MCLK (Output)
S3
SSI_BCLK (Output)
S5
S4
S4 S6
SSI_FS (Output)
S9 S10 S7 S7 S8 S8
SSI_FS (Input)
SSI_TXD
S9 S10
SSI_RXD
Figure 16. SSI Timing -- Master Modes
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 31
Electrical Characteristics
S11
SSI_BCLK (Input)
S15
S12 S12 S16
SSI_FS (Output)
S13
SSI_FS (Input)
S15
S14 S15 S16 S16
SSI_TXD
S17 S18
SSI_RXD
Figure 17. SSI Timing -- Slave Modes
5.12
I2C Timing Specifications
Table 18. I2C Input Timing Specifications between SCL and SDA
Num I1 I2 I3 I4 I5 I6 I7 I8 I9 Characteristic Start condition hold time Clock low period I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V) Data hold time I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V) Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time Min 2 8 -- 0 -- 4 0 2 2 Max -- -- 1 -- 1 -- -- -- -- Units tSYS tSYS ms ns ms tSYS ns tSYS tSYS
Table 18 lists specifications for the I2C input timing parameters shown in Figure 18.
Table 19 lists specifications for the I2C output timing parameters shown in Figure 18. Table 19. I2C Output Timing Specifications between SCL and SDA
Num I1
1
Characteristic Start condition hold time Clock low period I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V) Data hold time I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
Min 6 10 -- 7 --
Max -- -- -- -- 3
Units tSYS tSYS s tSYS ns
I21 I3 I4
2 1
I53
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 32 Freescale Semiconductor
Electrical Characteristics
Table 19. I2C Output Timing Specifications between SCL and SDA (continued)
Num I61 I71 I8
1
Characteristic Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time
Min 10 2 20 10
Max -- -- -- --
Units tSYS tSYS tSYS tSYS
I91
1
Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table 19. The I2C interface is designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual position is affected by the prescale and division values programmed into the IFDR. However, the numbers given in Table 19 are minimum values. 2 Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and pull-up resistor values. 3 Specified at a nominal 50-pF load.
I5 I2 I6
I2C_SCL
I1 I4 I7 I8 I3 I9
I2C_SDA
Figure 18. I2C Input/Output Timings
5.13
Fast Ethernet Timing Specifications
The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface.
5.13.1
Receive Signal Timing Specifications
Table 20. Receive Signal Timing
MII Mode RMII Mode Unit Min Max 25 -- -- 65% 65% Min -- 4 2 35% 35% Max 50 -- -- 65% 65% MHz ns ns RXCLK period RXCLK period --
1
The following timing specs meet the requirements for MII and 7-Wire style interfaces for a range of transceiver devices.
Num -- E1 E2 E3 E4
1
Characteristic RXCLK frequency RXD[n:0], RXDV, RXER to RXCLK setup RXCLK to RXD[n:0], RXDV, RXER hold1 RXCLK pulse width high RXCLK pulse width low
5 5 35% 35%
In MII mode, n = 3; In RMII mode, n = 1
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 33
Electrical Characteristics
RXCLK (Input)
E4
E3
E1
E2
RXD[n:0] RXDV, RXER
Valid Data
Figure 19. MII Receive Signal Timing Diagram
5.13.2
Transmit Signal Timing Specifications
Table 21. Transmit Signal Timing
MII Mode RMII Mode Unit Min Max 25 -- 25 65% 65% Min -- 5 -- 35% 35% Max 50 -- 14 65% 65% MHz ns ns tTXCLK tTXCLK -- 5 -- 35% 35%
Num -- E5 E6 E7 E8
1
Characteristic TXCLK frequency TXCLK to TXD[n:0], TXEN, TXER invalid1 TXCLK to TXD[n:0], TXEN, TXER TXCLK pulse width high TXCLK pulse width low valid1
In MII mode, n = 3; In RMII mode, n = 1
TXCLK (Input)
E6
E8
E7 E5
TXD[n:0] TXEN, TXER
Valid Data
Figure 20. MII Transmit Signal Timing Diagram
5.13.3
Num E9
Asynchronous Input Signal Timing Specifications
Table 22. MII Transmit Signal Timing
Characteristic CRS, COL minimum pulse width Min 1.5 Max -- Unit TXCLK period
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 34 Freescale Semiconductor
Electrical Characteristics
CRS, COL
E9
Figure 21. MII Async Inputs Timing Diagram
5.13.4
MII Serial Management Timing Specifications
Table 23. MII Serial Management Channel Signal Timing
Characteristic MDC cycle time MDC pulse width MDC to MDIO output valid MDC to MDIO output invalid MDIO input to MDC setup MDIO input to MDC hold
E10 E11
Num E10 E11 E12 E13 E14 E15
Symbol tMDC
Min 400 40 -- 25 10 0
Max -- 60 375 -- -- --
Unit ns % tMDC ns ns ns ns
MDC (Output)
E11 E12 E13
MDIO (Output)
Valid Data
E14
E15
MDIO (Input)
Valid Data
Figure 22. MII Serial Management Channel TIming Diagram
5.14
32-Bit Timer Module Timing Specifications
Table 24. Timer Module AC Timing Specifications
Name T1 T2 Characteristic DTnIN cycle time (n = 0:3) DTnIN pulse width (n = 0:3) Min 3 1 Max -- -- Unit tsys/2 tsys/2
Table 24 lists timer module AC timings.
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 35
Electrical Characteristics
5.15
ATA Interface Timing Specifications
The ATA controller is compatible with the ATA/ATAPI-6 industry standard. Refer to the ATA/ATAPI-6 Specficiation and the ATA controller chapter of the MCF54455 Reference Manual for timing diagrams of the various modes of operation. The timings of the various ATA data transfer modes are determined by a set of timing equations described in the ATA section of the MCF54455 Reference Manual. These timing equations must be fulfilled for the ATA host to meet timing. Table 25 provides implementation specific timing parameters necessary to complete the timing equations. Table 25. ATA Interface Timing Specifications1,2
Name A1 A2 A3 A4 A5 A6 A7
1 2
Characteristic Setup time -- ATA_IORDY to SYSCLK falling Hold time -- ATA_IORDY from SYSCLK falling Setup time -- ATA_DATA[15:0] to SYSCLK rising Propagation delay -- SYSCLK rising to all outputs Output skew Setup time -- ATA_DATA[15:0] valid to ATA_IORDY Hold time -- ATA_IORDY to ATA_DATA[15:0] invalid
Symbol tSUI tHI tSU tCO tSKEW1 tI_DS tI_DH
Min 4.0 3.0 4.0 -- -- 2.0 3.5
Max -- -- -- 7.0 1.5 -- --
Unit ns ns ns ns ns ns ns
Notes
3 3 4 4
These parameters are guaranteed by design and not testable. All timings specified with a capacitive load of 40pF. 3 Applies to ATA_CS[1:0], ATA_DA[2:0], ATA_DIOR, ATA_DIOW, ATA_DMACK, ATA_DATA[15:0] 4 Applies to Ultra DMA data-in burst only
5.16
DSPI Timing Specifications
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. Table 26 provides DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI chapter of the MCF54455 Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices. Table 26. DSPI Module AC Timing Specifications1
Name DS1 DS2 Characteristic DSPI_SCK Cycle Time DSPI_SCK Duty Cycle Symbol tSCK -- Min 4 x tSYS (tsck / 2) - 2.0 (2 x tSYS) - 1.5 (2 x tSYS) - 3.0 -- -5 9 0 Max -- (tsck / 2) + 2.0 Unit ns ns Notes
2 3
Master Mode DS3 DS4 DS5 DS6 DS7 DS8 DSPI_PCSn to DSPI_SCK delay DSPI_SCK to DSPI_PCSn delay DSPI_SCK to DSPI_SOUT valid DSPI_SCK to DSPI_SOUT invalid DSPI_SIN to DSPI_SCK input setup DSPI_SCK to DSPI_SIN input hold tCSC tASC -- -- -- -- -- -- 5 -- -- -- ns ns ns ns ns ns
4 5
Slave Mode DS9 DSPI_SCK to DSPI_SOUT valid -- -- 10 ns
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 36 Freescale Semiconductor
Electrical Characteristics
Table 26. DSPI Module AC Timing Specifications1 (continued)
Name DS10 DS11 DS12 DS13 DS14
1 2 3 4 5
Characteristic DSPI_SCK to DSPI_SOUT invalid DSPI_SIN to DSPI_SCK input setup DSPI_SCK to DSPI_SIN input hold DSPI_SS active to DSPI_SOUT driven DSPI_SS inactive to DSPI_SOUT not driven
Symbol -- -- -- -- --
Min 0 2 7 -- --
Max -- -- -- 10 10
Unit ns ns ns ns ns
Notes
Timings shown are for DMCR[MTFE] = 0 (classic SPI) and DCTARn[CPHA] = 0. Data is sampled on the DSPI_SIN pin on the odd-numbered DSPI_SCK edges and driven on the DSPI_SOUT pin on even-numbered DSPI edges. When in master mode, the baud rate is programmable in DCTARn[DBR], DCTARn[PBR], and DCTARn[BR]. This specification assumes a 50/50 duty cycle setting. The duty cycle is programmable in DCTARn[DBR], DCTARn[CPHA], and DCTARn[PBR]. The DSPI_PCSn to DSPI_SCK delay is programmable in DCTARn[PCSSCK] and DCTARn[CSSCK]. The DSPI_SCK to DSPI_PCSn delay is programmable in DCTARn[PASC] and DCTARn[ASC].
DS3
DS4
DSPI_PCSn
DS1 DS2
DSPI_SCK (DCTARn[CPOL] = 0)
DS2
DSPI_SCK (DCTARn[CPOL] = 1)
DS7 DS8
DSPI_SIN
First Data DS6
Data
Last Data
DS5 Data Last Data
DSPI_SOUT
First Data
Figure 23. DSPI Classic SPI Timing -- Master Mode
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 37
Electrical Characteristics
DSPI_SS
DS1
DSPI_SCK (DCTARn[CPOL] = 0)
DS2
DS2
DSPI_SCK (DCTARn[CPOL] = 1)
DS13 DS10 First Data DS11 DS12 Data Last Data Data DS9 Last Data
DS14
DSPI_SOUT
DSPI_SIN
First Data
Figure 24. DSPI Classic SPI Timing -- Slave Mode
5.17
SBF Timing Specifications
Table 27. SBF AC Timing Specifications
The Serial Boot Facility (SBF) provides a means to read configuration information and system boot code from a broad array of SPI-compatible EEPROMs, flashes, FRAMs, nVSRAMs, etc. Table 27 provides the AC timing specifications for the SBF.
Name SB1 SB2 SB3 SB4 SB5 SB6 SB7 SB8
1
Characteristic SBF_CK Cycle Time SBF_CK High/Low Time SBF_CS to SBF_CK delay SBF_CK to SBF_CS delay SBF_CK to SBF_DO valid SBF_CK to SBF_DO invalid SBF_DI to SBF_SCK input setup SBF_CK to SBF_DI input hold
Symbol tSBFCK -- -- -- -- -- -- --
Min 40 30% tSBFCK - 2.0 tSBFCK - 2.0 -5 5 10 0
Max -- -- -- -- -- -- -- --
Unit ns tSBFCK ns ns ns ns ns ns
Notes
1
At reset, the SBF_CK cycle time is tREF x 67. The first byte of data read from the serial memory contains a divider value that is used to set the SBF_CK cycle time for the duration of the serial boot process.
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 38 Freescale Semiconductor
Electrical Characteristics
SBF_CS
SB3 SB2 SB7 SB8 Data Last Data SB5 Data Last Data SB1 SB2 SB4
SBF_CK
SBF_DI
First Data SB6
SBF_DO
First Data
Figure 25. SBF Timing
5.18
General Purpose I/O Timing Specifications
Table 28. GPIO Timing1
Num G1 G2 G3 G4
1
Characteristic FB_CLK High to GPIO Output Valid FB_CLK High to GPIO Output Invalid GPIO Input Valid to FB_CLK High FB_CLK High to GPIO Input Invalid
Min -- 1.5 9 1.5
Max 9 -- -- --
Unit ns ns ns ns
These general purpose specifications apply to the following signals: IRQn, all UART signals, all timer signals, DACKn and DREQn, and all signals configured as GPIO.
FB_CLK
G1 G2
GPIO Outputs
G3 G4
GPIO Inputs
Figure 26. GPIO Timing
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 39
Electrical Characteristics
5.19
JTAG and Boundary Scan Timing
Table 29. JTAG and Boundary Scan Timing
Num J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14
1
Characteristics1 TCLK Frequency of Operation TCLK Cycle Period TCLK Clock Pulse Width TCLK Rise and Fall Times Boundary Scan Input Data Setup Time to TCLK Rise Boundary Scan Input Data Hold Time after TCLK Rise TCLK Low to Boundary Scan Output Data Valid TCLK Low to Boundary Scan Output High Z TMS, TDI Input Data Setup Time to TCLK Rise TMS, TDI Input Data Hold Time after TCLK Rise TCLK Low to TDO Data Valid TCLK Low to TDO High Z TRST Assert Time TRST Setup Time (Negation) to TCLK High
Min DC 50 20 -- 5 20 -- -- 4 10 -- -- 50 10
Max 20 -- 30 3 -- -- 33 33 -- -- 11 11 -- --
Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns
JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.
J2 J3 VIH J3
TCLK (input)
J4
VIL J4
Figure 27. Test Clock Input Timing
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 40 Freescale Semiconductor
Electrical Characteristics
TCLK
VIL J5
VIH J6
Data Inputs
J7
Input Data Valid
Data Outputs
J8
Output Data Valid
Data Outputs
J7
Data Outputs
Output Data Valid
Figure 28. Boundary Scan (JTAG) Timing
TCLK
VIL J9
VIH J10
TDI TMS
J11
Input Data Valid
TDO
J12
Output Data Valid
TDO
J11
TDO
Output Data Valid
Figure 29. Test Access Port Timing
TCLK
J14
TRST
J13
Figure 30. TRST Timing
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 41
Electrical Characteristics
5.20
Debug AC Timing Specifications
Table 30. Debug AC Timing Specification
Num D0 D1 D2 D3 D41 D5 D6
1
Table 30 lists specifications for the debug AC timing parameters shown in Figure 31 and Table 32.
Characteristic PSTCLK cycle time PSTCLK rising to PSTDDATA valid PSTCLK rising to PSTDDATA invalid DSI-to-DSCLK setup DSCLK-to-DSO hold DSCLK cycle time BKPT assertion time
Min 1 -- 1.5 1 4 5 1
Max 1 3.0 -- -- -- -- --
Units tSYS ns ns PSTCLK PSTCLK PSTCLK PSTCLK
DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input relative to the rising edge of PSTCLK.
D0
PSTCLK
D1 D2
PSTDDATA[7:0]
Figure 31. Real-Time Trace AC Timing
D5 DSCLK
D3
DSI
Current D4
Next
DSO
Past
Current
Figure 32. BDM Serial Port AC Timing
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 42 Freescale Semiconductor
Power Consumption
6
Power Consumption
Table 31. MCF4455 Application Power Consumption1
Core Freq. IVDD EVDD 266 MHz SDVDD Total Power IVDD EVDD 200 MHz SDVDD Total Power
1
All power consumption data is lab data measured on an M54455EVB running the Freescale Linux BSP.
Idle 215.6 27.6 142.9 672 163.8 29.9 142.2 601
MP3 Playback 288.8 33.6 158.2 829 228.0 34.7 158.5 742
TFTP Download 274.4 32.6 161.1 809 213.8 34.3 160.0 722
USB HS File Copy 263.7 32.4 158.0 787 207.9 33.8 153.4 699
Units
mA
mW
mA
mW
All voltage rails at nominal values: IVDD = 1.5 V, EVDD = 3.3 V, and SDVDD = 1.8 V.
850 800 750 700 650 600 550 500 Idle MP3 Playback
266 MHz
200 MHz
Total Power (mW)
TFTP Download USB HS File Copy
Figure 33. Power Consumption in Various Applications
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 43
Power Consumption
All current consumption data is lab data measured on a single device using an evaluation board. Table 32 shows the typical power consumption in low-power modes. These current measurements are taken after executing a STOP instruction. Table 32. Current Consumption in Low-Power Modes1,2
System Frequency Mode Voltage Supply IVDD (mA) Power (mW) WAIT/DOZE IVDD (mA) Power (mW) STOP 0 IVDD (mA) Power (mW) STOP 1 IVDD (mA) Power (mW) STOP 2 IVDD (mA) Power (mW) STOP 3
1
166 (Typ)3 93.4 140.1 28.0 42.0 17.1 25.7 17.9 26.8 5.7 8.6 1.8 2.6
200 (Typ)3 110.9 166.3 32.7 49.1 19.8 29.7 19.8 29.6 5.7 8.6 1.8 2.6
233 (Typ)3 128.2 192.4 37.5 56.2 22.5 33.7 22.4 33.6 5.7 8.6 1.8 2.6
266 (Typ)3 266 (Peak)4 145.4 218.1 41.1 61.7 25.2 37.8 25.1 37.6 5.7 8.6 1.8 2.6 202.1 303.2 100.2 150.3 25.2 37.8 25.1 37.6 5.7 8.6 1.8 2.6
RUN
IVDD (mA) Power (mW)
All values are measured on an M54455EVB with 1.5V IVDD power supply. Tests performed at room temperature. 2 Refer to the Power Management chapter in the MCF54455 Reference Manual for more information on low-power modes. 3 All peripheral clocks are off except UART0, INTC0, IACK, edge port, reset controller, CCM, PLL, and FlexBus prior to entering low-power mode. 4 All peripheral clocks on prior to entering low-power mode.
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 44 Freescale Semiconductor
Package Information
325.0 300.0 275.0
IVDD Power Consumption (mW)
250.0 225.0 Run 200.0 175.0 150.0 125.0 100.0 75.0 50.0 25.0 0.0 166 200 233 266 266 (peak) System Frequency (MHz)
Figure 34. IVDD Power Consumption in Low-Power Modes
Wait/Doze Stop 0 Stop 1 Stop 2 Stop 3
7
Package Information
The latest package outline drawings are available on the product summary pages on http://www.freescale.com/coldfire. Table 33 lists the case outline numbers per device. Use these numbers in the web page's keyword search engine to find the latest package outline drawings. Table 33. Package Information
Device MCF54450 256 MAPBGA MCF54451 MCF54452 MCF54453 360 TEPBGA MCF54454 MCF54455 98ARE10605D 98ARH98219A Package Type Case Outline Numbers
8
Product Documentation
Documentation is available from a local Freescale distributor, a Freescale sales office, the Freescale Literature Distribution Center, or through the Freescale world-wide web address at http://www.freescale.com/coldfire.
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 45
Revision History
9
Revision History
Table 34. Revision History
Table 34 summarizes revisions to this document.
Rev. No. 0 1
Date Sept 17, 2007 Initial public release.
Summary of Changes
Feb 15, 2008 Corrected VSS pin locations in MCF5445x signal information and muxing table for the 360 TEPBGA package: changed "...M9, M16, M17..." to "...M9-M14, M16..." Updated FlexBus read and write timing diagrams and added two notes before them. Change FB_A[23:0] to FB_A[31:0] in FlexBus read and write timing diagrams. Added power consumption section. May 1, 2008 In Family Configurations table, added PCI as feature on 256-pin devices. On these devices the PCI_AD bus is limited to 24-bits. In Absolute Maximum Ratings table, changed RTCVDD specification from "-0.3 to +4.0" to "-0.5 to +2.0". In DC Electrical Specifications table: * Changed RTCVDD specification from 3.0-3.6 to 1.35-1.65. * Changed High Impedance (Off-State) Leakage Current (IOZ) specification from 1 to 10A, and added footnote to this spec: "Worst-case tristate leakage current with only one I/O pin high. Since all I/Os share power when high, the leakage current is distributed among them. With all I/Os high, this spec reduces to 2 A min/max." Dec 1, 2008 Changed "360PBGA" heading to "360 TEPBGA" in Table 6. Changed the following specs in Table 13: * Minimum frequency of operation from -- to 60MHz * Maximum clock period from -- to 16.67 ns
2
3
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 46 Freescale Semiconductor
Revision History
MCF5445x ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 47
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Document Number: MCF54455
Rev. 3 12/2008

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